1. Field of the Invention
The present invention relates to an analog to digital convertor (hereinafter referred to as an A/D convertor) for converting an analog signal to a digital signal, and more particularly to a circuit constitution of an analog to digital convertor having high resolution.
2. Description of the Related Art
An A/D convertor of high resolution of 9 bits or more is demanded in recent years due to high integration and high density of a semiconductor device. This is for the purpose of processing various data digitally so as to reproduce them with high tone quality and high picture quality in various audio equipment, picture processing devices and so on.
For example, an N-bit flash type A/D convertor is composed of a plurality of reference resistors, comparators, logic circuits, encoders and so on. An analog signal is sampled, quantized and flash encoded flush based on a reference voltage. As a result, when, an A/D convertor of 9 bits or more is being constituted, each of the plurality of comparators for comparing the analog signal with the reference voltage have to be made to have a resolution of 9 bits or more. When an A/D convertor is presumed to be constituted by combining differential amplifiers of low resolution with one another, it is impossible to obtain an error in conversion-precision at .+-.0.5 [LSB] or less.
A related art example of an analog to digital convertor will now be described. For example, a flash type 9-bit A/D convertor is composed of 2.sup.N -2=510 reference resistors R1 to R510, 2.sup.N -1=511 comparators C1 to C511, 2.sup.N -1=511 two-input AND circuits (hereinafter referred to as NAND circuits) A1 to A511 and an encoder 1 and an output buffer 2. The reference resistors R1 to R510 are connected in series, and the resistor R1 is connected to a voltage source VRT. The resistor R510 is connected to a voltage source VRB.
The function of the above-described A/D convertor is such that, when 511 reference voltages V1 to V511 are generated by the reference resistors R1 to R510, an analog signal VIN is compared with reference voltage V1 based on a predetermined clock signal in the comparator C1 for instance, and the comparison signal is outputted to the NAND circuit A1. Further, in the comparator C2, the analog signal VIN and the reference voltage V2 are compared with each other, and the comparison signal thereof is outputted to two NAND circuits A1 and A2, respectively.
Furthermore, in the comparator C3, the analog signal VIN is compared with the reference voltage V3 based on the predetermined clock signal, and the comparison signal thereof is outputted to the NAND circuits A2 and A3, respectively.
In a similar manner thereafter, the analog signal VIN and the reference voltage V510 are compared with each other by the comparator C510, and the comparison signal thereof is outputted to the NAND circuits A509 and A510. Further, in the comparator C511, the analog signal VIN and the reference voltage V511 are compared with each other, and the comparison signal thereof is outputted to the NAND circuits A510 and A511.
With this, a digital output signal DOUT is generated in the encoder 1 based on the logical output values of 511 NAND circuits A1 to A511, and is amplified and outputted by the output buffer 2.